1. Field of the Invention
The present invention relates to a semiconductor device having a so-called SOI (silicon on insulator) structure in which a semiconductor layer is provided on an insulating surface.
2. Description of the Related Art
Integrated circuits using semiconductor substrates called silicon on insulator (hereinafter also referred to as “SOI”) in which a thin single-crystalline semiconductor layer is formed on an insulating surface instead of using silicon wafers that are manufactured by thinly slicing an ingot of a single-crystalline semiconductor are developed. The integrated circuits using the SOI substrates draw attention as semiconductor integrated circuits whose performance is improved by reduction of parasitic capacitance between a drain of a transistor and a substrate.
There are various manufacturing methods of SOI substrates, and an SOI substrate formed by a method called Smart Cut (registered trademark) is known as an SOI substrate which has achieved both quality of an SOI layer and easiness in production (throughput). This SOI substrate is formed in the following manner. Hydrogen ions are implanted to a bond wafer to form a silicon layer, and the bond wafer is bonded to another wafer (base wafer) at room temperature. Here, a strong bond is formed by van der Waals' forces and hydrogen bond at room temperature. Further, a covalent bond is formed by heat treatment at 400° C. to 700° C., so that the bond gets stronger. The silicon layer bonded to the base wafer is separated from the bond wafer by heat treatment at about 500° C.
As an example of semiconductor devices using such an SOI substrate, the applicant has disclosed the device in Reference 1 (Japanese Published Patent Application No. 2000-012864).